3d7105 monolithic 5-tap fixed delay line (series 3d7105) features packages 1 2 3 4 8 7 6 5 in o2 o4 gn d vd d o1 o3 o5 3d 7105z s oic ( 150 m i l ) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in n/ c n/ c o2 n/ c o4 n/ c gn d vd d n/ c n/ c o1 n/ c o3 n/ c o5 3d 71 05s s o l ( 300 m i l ) 8 7 6 5 1 2 3 4 in o2 o4 gn d vd d o1 o3 o5 3d 71 05 m d i p 3d 71 05 h g u ll- w in g 14 13 12 11 10 9 8 1 2 3 4 5 6 7 in n/c n/c o2 n/c o4 gnd vdd n/c o1 n/c o3 n/c o5 3d 7105 d i p 3d 7105g g u ll-w i ng 3d 7105k u n used pins remov ed ? all-silicon, low-power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? low ground bounce noise ? leading- and trailing-edge accuracy ? delay range: .75 through 80ns ? delay tolerance: 5% or 1ns ? temperature stability : 3% typical (0c-70c) ? vdd stability : 1% typical (4.75v-5.25v) ? minimum input pulse w i dth: 30% of total delay ? 14-pin dip and 16-pin soic available as drop-in f o r mechanical dimensions, click here . f o r package marking details, click here . replacements for hybrid delay lines functional description the 3d7105 5-tap delay line product fa mily consists of fixed-delay cmos integrated circuits. each pa ckage contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. tap-to-tap (incremental) delay values can r ange from 0.75ns through 8.0ns. the input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. the 3d7105 is ttl- and cmos- compatible, capable of driving t en 74ls-type loads, and features both rising- and falling-edge accuracy. the all-cmos 3d7105 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl fixed delay lines. it is offered in a standard 8-pin auto-insertable dip and a space saving surface mount 8-pin soic. pin descriptions in delay line input o1 tap 1 output (20%) o2 tap 2 output (40%) o3 tap 3 output (60%) o4 tap 4 output (80%) o5 tap 5 output (100%) vcc +5 volts gnd ground n/c no connection table 1: part number specifications pa rt number tolera nces input restrictions di p-8 3d 7105m 3d 7105h soic-8 3d 7105z dip-14 3d 7105 3d 7105g 3d 7105k soic-16 3d 7105s tota l dela y (ns) ta p-ta p dela y (ns) m ax operating fr equency ab s o l u t e m ax oper. freq. mi n operating pul se wi dth ab s o l u t e mi n oper. p.w. - . 7 5 - . 7 5 - . 7 5 - . 7 5 3.0 1.0* 0.75 0.4 41.7 mhz 166.7 mhz 12.0 ns 3.00 ns - 1 - 1 - 1 - 1 4.0 1.0* 1.0 0.5 37.0 mhz 166.7 mhz 13.5 ns 3.00 ns - 1 . 5 - 1 . 5 - 1 . 5 - 1 . 5 6.0 1.0* 1.5 0.7 30.3 mhz 166.7 mhz 16.5 ns 3.00 ns - 2 - 2 - 2 - 2 8.0 1.0* 2.0 0.8 25.6 mhz 166.7 mhz 19.5 ns 3.00 ns - 2 . 5 - 2 . 5 - 2 . 5 - 2 . 5 10.0 1.0* 2.5 1.0 22.2 mhz 133.3 mhz 22.5 ns 3.75 ns - 4 - 4 - 4 - 4 16.0 1.0* 4.0 1.3 15.9 mhz 83.3 mhz 31.5 ns 6.00 ns - 5 - 5 - 5 - 5 25.0 1.3 5.0 1.5 13.3 mhz 66.7 mhz 37.5 ns 7.50 ns - 8 - 8 - 8 - 8 40.0 2.0 8.0 1.5 9.52 mhz 41.7 mhz 52.5 ns 12.0 ns * total delay referenced to tap1 output; input-to-tap1 = 5.0ns 1.0ns note: a n y dash number betw een .75 and 8 not show n is also av ailable. ? 1996 data delay dev i ces doc #96006 data delay devices, inc. 1 8/7/2007 3 mt. prospect ave. clifton, nj 07013
3d7105 application notes operational description the 3d7105 five-tap delay line architecture is shown in figure 1. the delay line is composed of a number of delay cells connected in series. each delay cell produces at its output a replica of the signal present at its input, shifted in time. the delay cells are matched and share the same compensation signals, which minimizes tap-to- tap delay deviations over temperature and supply voltage variations. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3d7105 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number w ill include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3d7105 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number w ill include a vd d o1 in o2 o3 o4 t e m p & vd d c o m p en s a t i on gn d f i g u r e 1: 3d7105 func t i ona l d i a g r a m 25% 25% 25% 25% o5 vd d o1 in o2 o3 o4 t e m p & vd d c o m p en s a t i on gn d 20% 20% 20% 20% 20% o5 d a s h num be r s < 5 d a s h num be r s >= 5 doc #96006 data delay devices, inc. 2 8/7/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7105 doc #96006 data delay devices, inc. 3 8/7/2007 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy , if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d7105 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 600 ppm/c , which is equivalent to a variation , over the 0c-70c operating range, of 3% from the room-temperature delay settings and/or 1.0ns , whichever is greater. the pow er supply coefficient is reduced, over the 4.75v-5.25v operating range, to 1% of the delay settings at the nominal 5.0vdc power supply and/or 1.5ns , whichever is greater. it is essential that the pow er supply pin be adequately by passed and filtered. in addition, the pow er bus should be of as low an impedance construction as possible. pow e r planes are preferred. device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 . 0 1 . 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s static supply current* i dd 4 0 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih 1 a v ih = v dd low level input current i il 1 a v il = 0v high level output current i oh - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy namic) = 5 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/tap (pf) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz)
3d7105 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out 1 out 2 out 4 out 3 out tr i g in re f tr i g f i g u r e 2: t est s e t u p de v i ce unde r t est (d u t ) d i g i t a l sc o pe/ t i m e i n t e rv a l count e r pu l s e ge ne ra t o r com p ut e r sy st em pr in t e r in out 5 figur e 3 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l doc #96006 data delay devices, inc. 4 8/7/2007 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
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